Startup displays 7 bits per Flash memory cell with 10 years of retention

One of the key drivers for increasing capacity in next-generation storage was increasing the number of bits that can be stored per cell. A slight jump of one to two bits per cell gives a flat 100% increase, in exchange for more controls needed to read / write bits, but also limits cell endurance. We’ve seen storage commercialization of up to four bits per cell, and we’re talking about five. The Japanese company is now ready to start talking about its new 7-bit per cell solution.

Image courtesy of Plextor, up to 4 bits per cell

Switching from one to two bits per cell gives an easy doubling of capacity, and switching to three bits per cell is only a 50% increase. As more bits are added, the value of adding those bits decreases, but the cost of read and write control equipment increases exponentially. There must be a medium balance between how many bits per cell make economic sense and how much control electronics cost to enable those bits.

  • 1 bit per cell requires detection of 2 voltage levels, base capacity
  • 2 bits per cell requires detection of 4 voltage levels, + 100% capacity
  • 3 bits per cell requires detection of 8 voltage levels, + 50% capacity
  • 4 bits per cell requires detection of 16 voltage levels, + 33% capacity
  • 5 bits per cell requires detection of 32 voltage levels, + 25% capacity
  • 6 bits per cell requires detection of 64 voltage levels, + 20% capacity
  • 7 bits per cell requires detection of 128 voltage levels, + 16.7% capacity

Also, the more bits per cell, the less endurance – voltage variation when storing many bits only needs to deviate slightly to get the wrong result, so re-reading / writing to a high capacity cell will result in that voltage deviation. until the cell becomes unusable. Currently, the market seems satisfied with three bits per cell (3bpc) for performance and four bits per cell (4bpc) for capacity, with several 2bpc designs for long-term durability. Some of the largest vendors are working on 5bpc storage, although low endurance can make technology good only for WORM – write once, read a lot, which is a common abbreviation for the equivalent of something like an old school CD or a non-rewritable DVD.

Floadia Corp., a C-series startup from Japan, issued a press release this week stating that it has developed storage technology capable of seven bits per cell (7bpc). Back in the prototype phase, this 7bpc flash chip, probably in the WORM scenario, has an effective 10-year retention time at 150C. The company says that a standard modern memory cell with this level of control could sell data in only about 100 seconds, so the secret in the design is the new type of flash cell they developed.

The SONOS cell uses a distributed charge trap design that relies on a silicon oxide-nitride-silicon oxide schedule, and the company points to an efficient silicon nitride film in the environment where charges are trapped to allow high retention. In simple voltage programs and wipe cycles, the company displays 100k + cycles with very low voltage. Oxide-nitride-oxide layers rely on SiO2 and Si3N4, which is claimed to be easy to produce. This allows an unstable SONOS cell to be used in NV-SRAM or embedded designs, such as microcontrollers.

It’s actually that last point which means we’ve seen this in modern NAND flash for a long time since. Floadia is currently partnering with companies like Toshiba to implement a SONOS cell into various microcontrollers, instead of large NAND flash implementations, on a 40nm process node as a built-in flash IP with the properties of a computer in memory. They’re not yet at 7 bits per cell, in the sense that the company promotes that two cells can store up to 8 bits of network weights to conclude machine learning – when we get to 8 bits per cell, then that might be more applicable. 10-year retention of cell data is interesting, because embedded platforms will use fixed-weight algorithms over the life of the product, except for perhaps rare updates. Even with extended shelf life, Floadia does not go into detail about 7bpc cycling at this time.

Increasing from modern 3bpc to 6bpc NAND flash would allow a double increase in density, but larger cells would be needed, which would negate the benefits. There is also the performance aspect if development> 4bpc has ever reached the consumer, which is not touched.

It will be an interesting technology to follow.

Source: Floadie Press Release

Source link

Naveen Kumar

Friendly communicator. Music maven. Explorer. Pop culture trailblazer. Social media practitioner.

Related Articles

Leave a Reply

Your email address will not be published. Required fields are marked *

Back to top button