While not absolutely the first company on the market to talk about putting different types of silicon in the same packaging, AMD’s launch of the Ryzen 3000 in July 2019 was the first in bringing high-performance x86 computing through chipset media. The chipset paradigm worked very well for the company, having high-performance cores on optimized TSMC 7nm silicon, while translating multiple analog operations to cheaper GlobalFoundries 14nm silicon and building a high-speed interconnection between them. Compared to the monolithic design, AMD ultimately uses a better process for each feature, smaller chips that give better yields and binings, and packaging becomes the main cost collector. But how low can these chipboard designs be? I asked this question to AMD’s CEO Dr. Lisi Su.
In AMD’s consumer-focused product group, the only products it ships with chips are the Ryzen 3000 and Ryzen 5000 series high-performance processors. Their price ranges from $ 199 for a six-core Ryzen 5 3600, to $ 799 for a 16-core Ryzen 9 5950X.
Everything else focused on the consumer is one piece of silicon, not chips. Everything in AMD’s mobile portfolio relies on individual pieces of silicon, and they have also migrated to desktop forms in AMD’s desktop APU strategy. We see a clear line between where chips make financial sense and where they don’t. From AMD’s latest generation of processors, the Ryzen 5 5600X still costs $ 299 in retail.
One of the problems here is that the design of the chiplet requires additional packaging steps. The silicon that these processors are made of must lie in the PCB or the substrate, and depending on what you want to do with the substrate, it can affect its price. The design of the chipset requires high connection speeds between the chipset, as well as power and communication with the rest of the system. The act of placing a chiplet on a single substrate also has an effective cost, requiring accuracy – even if 99% of the exact placement per chiplet on the substrate means a product of 3 chips as a loss of yield of 3% of packaging, which increases costs. In addition, AMD must first ship its 14nm matrices for its products from New York to Asia, in order to package them with TSMC computer matrices, before shipping the final product worldwide. That could be reduced in the future, as AMD is ready to make its next-generation chipboard designs in Asia.
Finally, there must be a turning point where simply building a monolithic silicone product becomes better for the total cost than trying to send chips around and spending a lot of money on new packaging techniques. I asked the question of Dr. Lisa Su, acknowledging that AMD is not selling its latest generation for less than $ 300, is $ 300 a realistic turning point from the chipset to the chipless market.
Dr. Su explained how AMD architects look at their product design phases every possible way of joining chips. She explained what that meant monolithic, chip, packaging, process technologies, because the number of potential variables in all this has direct effects on the supply chain and costs and availability, as well as on the final performance of the product. Dr. Su summed up that it was AMD looking for what is best for performance, power, price – and what you say at a turning point can be true. Given this, dr. Su wanted her not to say directly that it was the norm, stating that she was I would expect in the future that the dynamics could change as silicon costs rise, as this changes that point of optimization. But it was clear in our discussions that it was AMD always looking at variables, with Dr. They end on a happy note to at at the right time, you will see chips at the bottom of the market.
Personally, I think it’s pretty telling that the market is very flexible with chips currently in the $ 300 + ecosystem. TSMC D0 yields N7 (and N5) are reportedly some of the best in the industry, which means that AMD’s mobile processors in the range of ~ 200 square mm can go off the production line and meet up to that value of $ 300 (and maybe some more than that). The increase leads to a limitation of the yield of the size of the mold, where the chips make sense. We are now at a stage where, if Moore’s Law continues, how many calculations can we fit into that 200 square mm silicon and which markets can benefit from it – or we will get to the point where many more functions are added to make sizes silicon increased, necessarily pushing everything down the path of the chips. During the discussion, Dr. Su mentioned economies of scale when it comes to packaging, so it will be interesting to see how this dynamic shakes up. But for now, it seems that AMD’s way of dealing with the market below $ 300 will be with the latest generation hardware or monolithic silicone.
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