Despite most of the discussions about chip production focused on the leading and astonishingly fast and complex side of the industry, the demand for “inherited” process technologies is also higher than ever, but also much higher in volume than the latest and largest. These inherited processes form the backbone of most modern electronics, so the ability to offer equivalent technologies at a lower cost / power is often a win-win for chip manufacturers and designers. To that end, Samsung is announcing a new 17nm process node, designed for users who still use the planar 28nm process but want to take advantage of 14nm FinFET technology.
In modern processor design, a production process node comes with a set of design rules. To design a chip on that node, you must follow these design rules. Usually, these rules will have absolute limitations in the worst case, but if the chip designer can use the limitations to optimize his product, then it is useful to be closely acquainted with what can or cannot be done. As a result, a process like Samsung’s 28 nm that uses planar transistors will have a set of design rules different from Samsung’s 14 nm, which uses 3D FinFET transistors. The design rules also take into account where to put the power, connectivity, all the way to the metal array from the transistor to the contact pads for the packaging.
In terms of production, at a high level there are two or three main segments to consider. The front end of the line (FEOL) starts the production of circuits, designing transistors. When we talk about the latest technologies, the FEOL section inherently applies, because we need better and better tools to make ever smaller details in silicon to get the best transistors. After FEOL makes multiple layers with the transistors, the board is moved to the background line (BEOL) for the rest of the circuit — BEOL takes care of laying the layers of connecting wires, power supply and all auxiliary connections. After BEOL, the chips go for testing, cutting (into cubes), and then packaging.
Sometimes the term Middle-of-Line or Middle-End-of-Line (MEOL) is used for silicon pass-through (TSV) chips designed to stack multiple chips.
At the holistic level, FEOL and BEOL of any process node, say 28nm, have a 28nm version of the design rules for both of these segments. Sometimes manufacturers will combine one set of design rules on FEOL with another on BEOL to produce a new product line, with some features of both. This is what Samsung is doing with its new 17nm / 17LPV (Low Power Value) process, announced today as part of Samsung’s Foundry Forum event.
17LPV will combine 14nm FEOL, so efficient 14nm FinFET transistors, with 28nm BEOL for connection. This means that users can benefit from the performance / power of FinFET design at an additional cost, at no additional cost of denser BEOL. Finally, the size of the matrix is probably still determined by the larger BEOL node, but lower power transistors appear to be in demand. Samsung claims that 17LPV will reduce the matrix surface area by more than 43%, 39% better performance or 49% increase energy efficiency compared to the traditional 28 nm process.
The first application for 17LPV will be in camera image signal processors, as part of Samsung’s portfolio of CMOS image sensors. These chips do not necessarily require density, which makes 17LPV a good fit, but optimized power and cost will benefit the specialized technology involved in stacking. In addition, Samsung integrates 17LPV into its high-voltage offering, targeting DDIC / display drivers that require high-voltage background support combined with logic enhancements.
In addition to the 17LPV, Samsung Foundry creates a 14LPU (we think it’s still 28nm BEOL + 14nm FEOL) or Low Power Ultimate, for use with built-in MRAM and microcontrollers.
The exact timelines of this new node have not yet been revealed, although Samsung Foundry has called the node part of a ‘paradigm shift’ within the company when it comes to developing new solutions for specific processes for these markets.
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